Operational amplifiers (op amps) have differential inputs that are substantially unresponsive to common mode voltages. Their outputs are typically single ended and their open loop voltage gain is very high. The input stage is typically a differential transistor pair that is supplied with a constant tail current. This means that the total current flowing in the transistor input pair is constant but the currents in the individual transistor can be modulated differentially.
If a differential to single ended signal conversion is to be accomplished it is often done in the input stage. This is typically achieved by coupling a current mirror load to the transistor input pair. U.S. Pat. No. 4,528,496 by Toyojiro Naokawa and Matsuro Koterasawa is assigned to the Assignee of the present invention. It teaches the basic current mirror circuits and its teaching is incorporated herein by reference. If a simple current mirror is employed, the diode-connected transistor presents a relatively low impedance to the differential pair and low voltage gain results. Also, the accuracy of the current mirror is dependent upon transistor Beta.
The Wilson current mirror does much to correct this and is in common use in op amps. The Wilson circuit has high accuracy in that its operation is much less dependent on transistor Beta and its output impedance is much higher.
Another useful current mirror load circuit, called a super diode mirror, employs a pair of active transistors and an emitter follower coupled between the collector and base of one of the transistors provides for the differential to single ended conversion. This kind of load circuit provides high accuracy and has high output impedance.
However, all of the above load circuits require the connection of a high imput impedance buffer to the current mirror load. This connection involves either the base of a common emitter amplifier stage or the base of an emitter follower buffer. In either case the succeeding stage output will typically involve a substantial signal voltage swing. Since this voltage variation will be reflected back through the stage it will result in a variable load on the transistor input pair.